Browse Dissertations and Theses - Electrical and Computer Engineering by Contributor "Patel, Sanjay J."

  • Venshtain, Simion (2011-05-25)
    Memory model design is a major part of any modern processor architecture. There are many design choices and tradeoffs to be considered, and these often need to be tightly coupled to the processing unit's arcitecure. The ...

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  • Wang, Nicholas J. (2007)
    Finally, in this work, pains were taken to include as much detail as possible in the processor model and analysis methodology. We conclude with an examination of how making various approximations in the model and analysis ...

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  • Sung, I-Jui (2013-05-24)
    Matrix transposition is an important algorithmic building block for many numeric algorithms like multidimensional FFT. It has also been used to convert the storage layout of arrays. Intuitively, in-place transposition ...

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  • Truty, Wojciech J. (2010-06-22)
    Scientific applications rely heavily on floating point data types. Floating point operations are complex and require complicated hardware that is both area and power intensive. The emergence of massively parallel ...

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  • Cheng, Zuofu (2014-09-16)
    Current-generation video game applications use sampled recordings along with positional audio and modular effects to create the audio experience. While computationally efficient, this presents multiple immersion and game ...

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  • Lefever, Ryan M. (2011-05-25)
    An important approach for software dependability is the use of diversity to detect and/or tolerate errors. We develop and evaluate an approach for automated program diversity called Diverse Partial Memory Replication ...

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  • Fahs, Brian Matthew (2005)
    On a broad level, we describe the relationship between well-known compiler optimization concepts and hardware-implemented optimizations. We define and explore two hardware-centric dynamic optimization paradigms: continuous ...

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    application/pdfPDF (7MB)Restricted to U of Illinois
  • Crago, Neal (2011-05-25)
    We present Outrider, an architecture for throughput-oriented processors that exploits intra-thread memory-level parallelism (MLP) to improve performance efficiency on highly threaded workloads. Outrider enables a single ...

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  • Crago, Neal (2012-09-18)
    This dissertation presents a novel decoupled latency tolerance technique for 1000-core data parallel processors. The approach focuses on developing instruction latency tolerance to improve performance for a single thread. ...

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  • Johnson, Daniel R. (2011-05-25)
    In this thesis, I describe the evaluation framework for Rigel, a 1024-core single-chip accelerator architecture designed for high throughput on visual computing and scientific workloads. I present an integrated ...

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  • Wagner, Andrew (2012-02-06)
    Many classic and contemporary face recognition algorithms work well on public data sets, but degrade sharply when they are used in a real recognition system. A major cause of this is the difficulty of simultaneously handling ...

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  • Johnson, Matthew Robert (2015-04-24)
    Power and energy consumption have become important for all computers, but the tools used to measure and optimize power on physical hardware lag far behind performance focused tools. Existing measurement apparata have low ...

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  • Johnson, Matthew (2013-05-24)
    A system’s memory access control mechanisms profoundly impact the performance, reliability, security, and composability of the software it runs. Desirable features of an access control mechanism include: the ability to ...

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  • Kelm, John H. (2011-01-14)
    This work describes a cache architecture and memory model for 1000+ core microprocessors. Our approach exploits workload characteristics and programming model assumptions to build a hybrid memory model that incorporates ...

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  • Johnson, Daniel (2013-05-28)
    This dissertation describes work on the architecture of throughput-oriented accelerator processors. First, we examine the limitations of current accelerator processors and identify an opportunity to enable high ...

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  • Kong, Hui (2011-01-14)
    As IC technology advances rapidly, the dimensions of packages and PCBs are decreasing while the pin counts and routing layers keep increasing. Today, a high-performance PCB usually contains thousands of pins and more than ...

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  • Karpuzcu, Rahmet (2012-09-18)
    Ideal CMOS device scaling relies on scaling voltages down with lithographic dimensions at every technology generation. This gives rise to faster circuits due to higher frequency and smaller silicon area for the same ...

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  • Hussain, Ali A. (2011-05-25)
    With the trend towards parallel processing in computing, interest is developing in enabling workloads to be done at faster speeds to enable new usage models. SIFT is an algorithm for image detection and can be used for a ...

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  • Meyer, Gregory Paul (2016-11-22)
    We present a method for real-time 3D face localization and verification using a consumer-grade depth camera. Our approach consists of three parts: face detection, head pose estimation, and face verification. Face detection ...

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  • Agrawal, Aditya (2015-01-21)
    An effective approach to reduce the static energy consumption of large on-chip memories is to use a low-leakage technology such as embedded DRAM (eDRAM). Unfortunately, eDRAM, being a dynamic memory, requires periodic ...

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