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Title:Modeling and Design Space Exploration for Memory Hierarchy
Author(s):Umenthum, Kenny
Contributor(s):Chen, Deming
Subject(s):memory hierarchy
cache
modeling
optimization
Abstract:Memory hierarchy is one of two dominating resource costs (power, latency, area) in system-on-chip designs, the other being the processors and co-processors themselves, and in some applications, memory is the dominating cost. Design choices in the memory hierarchy, the software-hardware partitioning, and the optimization of those hardware and software components all affect the final power, latency, and area costs of a chip in a cross-dependent manner. Even after design space pruning, software-hardware partitioning with software and hardware optimization may result in hundreds of possibly optimal design points. Each point must consider a large number of memory hierarchy designs to come up with a complete and accurate optimal cost/performance trade-off curve. To attack this large-scale combinatorial optimization problem, methods for efficiently modeling and pruning the design space of memory hierarchy in the context of hardware-software co-design for system-on-chip are presented.
Issue Date:2015-12
Genre:Other
Type:Text
Language:English
URI:http://hdl.handle.net/2142/88913
Date Available in IDEALS:2016-02-22


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