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Title:Design of reliable and energy-efficient high-speed interface circuits
Author(s):Keel, Min-Sun
Director of Research:Rosenbaum, Elyse
Doctoral Committee Chair(s):Rosenbaum, Elyse
Doctoral Committee Member(s):Hanumolu, Pavan Kumar; Schutt-Aine, Jose E.; Shanbhag, Naresh R.
Department / Program:Electrical & Computer Engineering
Discipline:Electrical & Computer Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Electrostatic discharge (ESD)
Charged device model (CDM)
High-speed I/O
wireline communication
ADC-based receiver
Stub Series Terminated Logic (SSTL)
Abstract:The data-rate demand in high-speed interface circuits increases exponentially every year. High-speed I/Os are better implemented in advanced process technologies for lower-power systems, with the advantages of improved driving capability of the transistors and reduced parasitic capacitance. However, advanced technologies are not necessarily advantageous in terms of device reliability; in particular device failure from electrostatic discharge (ESD) becomes more likely in nano-scale process nodes. In order to secure ESD resiliency, the size of ESD devices on I/O pads should be sufficiently large, which may potentially reduce I/O speed. These two conflicting requirements in high-speed I/O design sometimes require sacrifice to one of the two properties. In this dissertation, three different approaches are proposed to achieve reliable and energy-efficient interface circuits. As the first approach, a novel ESD self-protection scheme to utilize “adaptive active bias conditioning” is proposed to reduce voltage stress on the vulnerable transistors, thereby reducing the burden on ESD protection devices. The second approach is to cancel out effective parasitic capacitance from ESD devices by the T-coil network. Voltage overshoot generated by magnetic coupling of the T-coil network can be suppressed by the proposed “inductance halving” technique, which reduces mutual inductance during ESD. The last approach employs system-level knowledge in the design of an ADC-based receiver for high intersymbol interference (ISI) channels. As a system-level performance metric, bit-error rate (BER) is adopted to mitigate a bit-resolution requirement in “BER-optimal ADC”, which can lead to 2× power-efficiency in the flash ADC and achieve a better BER performance.
Issue Date:2015-08-10
Rights Information:Copyright 2015 Min-Sun Keel
Date Available in IDEALS:2016-03-02
Date Deposited:2015-12

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