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Title:Architectural & circuit level techniques to improve energy efficiency of high speed serial links
Author(s):Saxena, Saurabh
Director of Research:Hanumolu, Pavan Kumar
Doctoral Committee Chair(s):Hanumolu, Pavan Kumar
Doctoral Committee Member(s):Shanbhag, Naresh R; Schutt-Aine, Jose; Viswanath, Pramod
Department / Program:Electrical & Computer Engineering
Discipline:Electrical & Computer Engineering
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:Ph.D.
Genre:Dissertation
Subject(s):Serial links
Time-based equalization
Charge-based flip-flop
Charge-based data demultiplexer (DMUX)
Clock & data recovery
Partially-segmented VM output driver
Abstract:High performance computing and communication are two key aspects of all information processing systems. With aggressive scaling of silicon technology enabling integration of a large number of transistors in a small area, managing power and thermal reliability has become very challenging. While lowering the power needed for performing computation has been the prime focus for decades, energy consumed for data transfer has recently become a major bottleneck especially in high performance applications. The focus of this thesis is on improving energy efficiency of communication links by exploring design techniques at both the architectural and circuit levels. In the first part of this work, we propose a time-based equalization scheme to implement transmit de-emphasis in voltage-mode output drivers. Using two-level pulse-width modulation, it overcomes the tradeoff between impedance matching, output swing, and de-emphasis resolution in conventional voltage-mode drivers. A prototype PWM-based 5$\,$Gb/s voltage-mode transmitter was implemented in a 90$\,$nm CMOS process and characterized across different channels and output swings to demonstrate the effectiveness of proposed techniques. The horizontal/vertical eye openings (BER=$\rm 10^{-12}$) at the ends of 60$\,$inch and 96$\,$inch stripline channels are 78$\,$mV/0.6$\,$UI and 8$\,$mV/0.3$\,$UI, respectively. This transmitter achieves an energy efficiency of 3.1$\,$mW/Gb/s while compensating for 16-28$\,$dB channel loss, which compares favorably with the state-of-the-art. In the second part, techniques to improve energy efficiency of a complete transceiver are presented. The transmitter employs a novel partially segmented voltage-mode output driver to lower power consumption in pre-drivers during 2-tap FIR equalization. The receiver implements a low power half-rate clock and data recovery with the proposed ring PLL based multi-phase sampling clock generation in CDR loop and charge-based sampling and deserialization. These techniques are verified using the measured results obtained from a 14Gb/s transceiver prototype. Transmitter achieves an energy efficiency of 0.89$\,$mW/Gb/s while securing a 0.36$\,$UI sampling time margin with $\rm{BER=10^{-12}}$ at the end of the channel with 11$\,$dB loss at Nyquist frequency. The receiver recovers sampling clock with 1.8$\,$$\rm{ps_{rms}}$ long term absolute jitter while recovering 14$\,$Gb/s data at $\rm{BER=10^{-12}}$. The receiver achieves an energy efficiency of 1.69$\,$mW/Gb/s. Transmitter and receiver share an LC PLL, which achieves 0.605$\,$$\rm{ps_{rms}}$ integrated jitter at 7$\,$GHz output with an energy efficiency of 0.5$\,$mW/GHz. The transceiver as a whole achieves an energy efficiency of 2.8$\,$mW/Gb/s.
Issue Date:2015-11-18
Type:Thesis
URI:http://hdl.handle.net/2142/89202
Rights Information:Copyright 2015 Saurabh Saxena
Date Available in IDEALS:2016-03-02
Date Deposited:2015-12


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