Files in this item

FilesDescriptionFormat

application/pdf

application/pdfWANG-THESIS-2016.pdf (2MB)
(no description provided)PDF

Description

Title:Time-based low dropout regulator
Author(s):Wang, Danyang
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):Low dropout regulator
Analog
Abstract:The low dropout regulator (LDO) is an essential building block for modern integrated circuits. Traditional analog design faces formidable challenges as technology scales down, such as lower supply voltage and channel length modulation. Digital LDOs do not have the problems that analog LDOs have, but they usually have worse performance metrics. Therefore, a time-based LDO is proposed to combine the merits of both analog and digital together. In the end, the LDO achieves 0.6-1 V supply voltage range and 0.5-0.9 V output voltage range. The maximum output current is 50 mA and the worst case transient time is 1.58 μs under 0.6 V supply voltage. The maximum current efficiency is 99.98%.
Issue Date:2016-04-27
Type:Thesis
URI:http://hdl.handle.net/2142/90671
Rights Information:Copyright 2016 Danyang Wang
Date Available in IDEALS:2016-07-07
Date Deposited:2016-05


This item appears in the following Collection(s)

Item Statistics