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Title:Design and implementation of a phase locked loop for high-speed serial links
Author(s):Mehta, Rushabh Ravindra
Advisor(s):Schutt-Ainé, José
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Phase-Locked Loops (PLL)
High-Speed Serial Links
Serial Links
Abstract:Recent advances in the semiconductor industry and process technology scaling have increased the demand for fast, robust computing. The thirst for high-processing, low power ICs is ever increasing. This has pushed the demand for high data rates in wireless and wireline communication systems in the multi-Gbps range. With higher data rates, the I/O links need to scale proportionally. However, the I/O channel bandwidth has not scaled appropriately making it the biggest bottleneck in high-speed links. Parallel links have not been able to match this increasing system performance due to issues such as crosstalk, timing skew and packaging costs. Thus there is a need for high-speed serial links. For high-speed transmission of data, there arises a need for high-speed on chip clocking circuits making the use of Phase-Locked Loops (PLLs) imperative. This thesis includes an overview of high-speed links along with the need for PLLs. An in-depth understanding of PLL theory, loop dynamics and behavioral and transistor level simulation follows. Performance metrics such as phase noise, random jitter and deterministic jitter are discussed. Finally, this thesis concludes with an insight into All Digital Phase-Locked Loops (ADPLLs).
Issue Date:2016-04-27
Rights Information:Copyright 2016 Rushabh Mehta
Date Available in IDEALS:2016-07-07
Date Deposited:2016-05

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