Files in this item

FilesDescriptionFormat

application/pdf

application/pdfECE499-Sp2016-park.pdf (798kB)Restricted to U of Illinois
(no description provided)PDF

Description

Title:Design and analysis of ultra low power phase locked loop
Author(s):Park, Seong Ho
Contributor(s):Hanumolu, Pavan Kumar
Degree:B.S. (bachelor's)
Genre:Thesis
Subject(s):internet of things
ultra low power
phase locked loop
Abstract:With the rising demand of Internet of Things devices, ultra low power systems recently have been a popular research topic; however, such systems have characteristically large power consumption. In response to this issue, an ultra low power phase locked loop is studied. This work includes analysis of a conventional phase locked loop, derivation of component parameters, proposal of an ultra low power phase locked loop architecture that consumes 92.75 nW at 15.4 MHz of oscillation with 500 mV supply voltage.
Issue Date:2016-05
Genre:Dissertation / Thesis
Type:Text
Language:English
URI:http://hdl.handle.net/2142/91558
Date Available in IDEALS:2016-08-30


This item appears in the following Collection(s)

Item Statistics