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Title:FPGA-Targeted High-Level Binding Algorithm for Power and Area Reduction with Glitch-Estimation
Author(s):Cromar, Scott A.; Chen, Deming; Lee, Jaeho
high-level synthesis
glitch power
power reduction
Abstract:Glitches (i.e. spurious signal transitions) are major sources of dynamic power consumption in modern FPGAs. In this paper, we present an FPGA-targeted, glitch-aware, high-level binding algorithm for power and area reduction, accomplished via dynamic power estimation and multiplexer balancing. Our binding algorithm employs a glitch-aware dynamic power estimation technique derived from the FPGA technology mapper in [6]. High-level binding results are converted to VHDL, and synthesized with Altera’s Quartus II software, targeting the Cyclone II FPGA architecture. Power characteristics are evaluated with the Altera PowerPlay Power Analyzer. The binding results of our algorithm are compared to LOPASS, a state-of-the-art low-power high-level synthesis algorithm for FPGAs. Experimental results show that our algorithm, on average, reduces toggle rate by 22% and area by 9%, resulting in a decrease in dynamic power consumption of 19%. To the best of our knowledge this is the first high-level binding algorithm targeting FPGAs that considers glitch power.
Issue Date:2009-01-17
Citation Info:DAC '09: Proceedings of the 46th Annual Design Automation Conference, July 2009.
Genre:Conference Paper / Presentation
Publication Status:published or submitted for publication
Peer Reviewed:is peer reviewed
Rights Information:© ACM, 2009. This is the author's version of the work. It is posted here by permission of ACM for your personal use. Not for redistribution. The definitive version was published in DAC '09: Proceedings of the 46th Annual Design Automation Conference, 2009
Date Available in IDEALS:2009-01-17

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