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VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip

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Title: VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip
Author(s): Akram, Shoaib; Cromar, Scott A.; Lucas, Gregory; Papakonstantinou, Alexandros; Chen, Deming
Subject(s): integrated circuit design system-on-chip application-specific multicore deep submicron technology error-resilient computation holistic error modeling onchip parameter variations soft-hard errors variation-aware synthesis
Abstract: Billions of devices on a chip is around the corner and the trend of deep submicron (DSM) technology scaling will continue for at least another decade. Meanwhile, designers also face severe on-chip parameter variations, soft/hard errors, and high leakage power. How to use these billions of devices to deliver power-efficient, high-performance, and yet error-resilient computation is a challenging task. In this paper, we attempt to demonstrate some of our perspectives to address these critical issues. We elaborate on variation-aware synthesis, holistic error modeling, reliable multicore, and synthesis for application-specific multicore. We also present some of our insights for future reliable computing.
Issue Date: 2008-04-08
Publisher: IEEE
Citation Info: IEEE/ACM Asia and South Pacific Design Automation Conference, January 2008
Genre: Conference Paper / Presentation
Type: Text
Language: English
DOI: 10.1109/ASPDAC.2008.4484062
Publication Status: published or submitted for publication
Peer Reviewed: is peer reviewed
Rights Information: ©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Date Available in IDEALS: 2009-03-03

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