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Title:Successive-approximation-register based quantizer design for high-speed delta-sigma modulators
Author(s):Shah, Aarti Mahesh Kumar
Advisor(s):Radhakrishnan, Chandrasekhar
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Degree:M.S.
Genre:Thesis
Subject(s):analog-to-digital converters
high speed SAR, SAR ADC design
delta-sigma modulators
quantizer
medium resolution SAR
TI SAR
time interleaved ADC
higher order delta-sigma modulator design
delta-sigma simulink models
Abstract:High-speed delta-sigma modulators are in high demand for applications such as wire-line and wireless communications, medical imaging, RF receivers and high-definition video processing. A high-speed delta-sigma modulator requires that all components of the delta-sigma loop operate at the desired high frequency. For this reason, it is essential that the quantizer used in the delta-sigma loop operate at a high sampling frequency. This thesis focuses on the design of high-speed time-interleaved multi-bit successive- approximation-register (SAR) quantizers. Design techniques for high-speed medium-resolution SAR analog-to-digital converters (ADCs) using synchronous SAR logic are proposed. Four-bit and 8-bit 5 GS/s SAR ADCs have been implemented in 65 nm CMOS using 8-channel and 16-channel time-interleaving respectively. The 4-bit SAR ADC achieves SNR of 24.3 dB, figure-of-merit (FoM) of 638 fJ/conversion-step and 42.6 mW power consumption, while the 8-bit SAR ADC achieves SNR of 41.5 dB, FoM of 191 fJ/conversion-step and 92.8 mW power consumption. High-speed operation is achieved by optimizing the critical path in the SAR ADC loop. A sampling network with a split-array with unit bridge capacitor topology is used to reduce the area of the sampling network and switch drivers.
Issue Date:2017-04-25
Type:Thesis
URI:http://hdl.handle.net/2142/97465
Rights Information:Copyright 2017 Aarti Mahesh Kumar Shah
Date Available in IDEALS:2017-08-10
Date Deposited:2017-05


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