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FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization

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Title: FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization
Author(s): Lucas, Gregory; Cromar, Scott A.; Chen, Deming
Subject(s): high-level synthesis behavioral synthesis performance yield high-level binding variation-aware process variation
Abstract: While technology scaling has presented many new and exciting opportunities, new design challenges have arisen due to increased density, and delay and power variations. High level synthesis has been touted as a solution to these problems, as it can significantly reduce the number of man hours required for a design by raising the level of abstraction. In this paper, we propose a new variation-aware high-level synthesis binding/module selection algorithm, named FastYield, which takes into consideration multiplexers, functional units, registers, and interconnects. Additionally, FastYield connects with the lower levels of the design hierarchy through its inclusion of a timing driven floorplanner guided by a statistical static timing analysis (SSTA) engine which is used to modify/enhance the synthesis solution. FastYield is able to incorporate spatial correlations of process variations in its optimization, which are shown to affect performance yield. On average, FastYield achieves a clock period that is 14.5% smaller, and a performance yield gain of 78.9%, when compared to a variation-unaware algorithm. By making use of accurate timing information, FastYield’s rebinding improves performance yield by an average of 9.8% over the initial binding, for the same clock period. To the best of our knowledge, this is the first high-level synthesis binding/module selection algorithm that is layout-driven and variation aware.
Issue Date: 2009-01
Publisher: IEEE
Citation Info: IEEE/ACM Asia and South Pacific Design Automation Conference, January 2009
Genre: Conference Paper / Presentation
Type: Text
Language: English
URI: http://hdl.handle.net/2142/9763
Publication Status: published or submitted for publication
Peer Reviewed: is peer reviewed
Rights Information: © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Date Available in IDEALS: 2009-03-18
 

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