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Title:Miniaturization of on-chip passive electronic devices by silicon nitride self-rolled-up membrane microtube nanotechnology
Author(s):Huang, Wen
Director of Research:Li, Xiuling
Doctoral Committee Chair(s):Li, Xiuling
Doctoral Committee Member(s):Rogers, John A.; Lyding, Joseph W.; Gong, Songbin
Department / Program:Electrical & Computer Eng
Discipline:Electrical & Computer Engr
Degree Granting Institution:University of Illinois at Urbana-Champaign
Subject(s):Self-rolled-up membrane
Silicon nitride
Power electronics
Abstract:Miniaturization of the commonly used on-chip lumped elements is highly desirable to enhance the density, performance and functionality of integrated circuits (ICs) working from DC to millimeter wave frequency band. Numerous improvement methods have been demonstrated but all fail to fundamentally solve the intrinsic drawbacks of currently used planar spiral platforms for passive lumped elements. A new design platform based on self-rolled-up membrane (S-RuM) nanotechnology that “processes like 2-D and functions like 3-D” is proposed for constructing on-chip three-dimensional (3-D) rolled-up microtube structures. By taking lumped inductors and transformers, this thesis demonstrates a global solution to obtain on-chip lumped elements with an extremely small on-chip footprint and almost complete immunity to substrate issues. The fabrication process of S-RuM lumped elements is designed to be CMOS compatible with a clear trend to achieving 100% fabrication yield. A quasi-dynamic finite element method (FEM) is established to precisely calculate the dimensions of rolled-up structures, which allows an accurate simulation of the electrical performance of S-RuM lumped passive devices by physical modeling. The design of the S-RuM inductor from FEM structural simulation to physical model electrical simulation is demonstrated, and its physical model is further integrated into the commercial Advanced Design System (ADS) software as a design kit for circuit-level simulation. Full wave FEM 3-D modeling of ICs including S-RuM inductors in the layouts is enabled by EMPro and ADS FEM co-simulation. A simple high pass filter is used as an example to show the S-RuM IC design process. A clear trend to save 38% ~ 50% chip size is also shown in active IC examples by replacing planar spiral inductors with S-RuM inductors. As a unit device, the S-RuM inductor can be used to build other passive elements like transformers. So, the S-RuM transformer is also investigated in this thesis. The thermal and mechanical reliability of the S-RuM platform are tested by using rapid thermal annealing (RTA) and nano-indention, which provide data for further packaging S-RuM lumped passive devices and applications in a power electronics. All samples are fabricated on a 1 to 10 cm p-type silicon substrate. Cu based S-RuM inductor samples show a 119 nH/mm2 inductance density, Q factor of 3 @ 8 GHz, a 0.3 nH to 2.4 nH inductance range, a self-resonant-frequency (SRF) of ~20 GHz, 250 C thermal stability, and 48.6 N/m stiffness. Au based S-RuM transformer samples shows a 1.52:1 turn ratio (n), 0.99 mutual magnetic coupling coefficient (km), and 0.392 maximum available gain at 8.6 GHz with a footprint (S) of only ~0.0085 mm2. The corresponding index of transformer performance ((n∙ km)/S ) is 177, which is ~2 than that of the best on-chip planar transformer reported so far with a similar turn ratio. The performance of the S-RuM transformers is stable at temperatures up to 250 ºC, and the hardness of the rolled-up structures is as high as 270.2 N/m.
Issue Date:2017-04-19
Rights Information:Copyright 2017 Wen Huang
Date Available in IDEALS:2017-08-10
Date Deposited:2017-05

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