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Title:Design and Simulation of a Charge-Pump Phase-Locked Loop in 65 nm CMOS Technology
Author(s):Rajwardan, Ashwarya
Contributor(s):Schutt-Aine, Jose
Subject(s):PLL
VCO
Charge Pump
Phase and Frequency Detector
PFD
TSPC
Divide Counter
Abstract:This thesis gives a brief overview of a basic PLL circuit and reports the in-depth analysis of the design procedure and working of a charge-pump phase-locked loop (PLL) in 65 nm CMOS technology. The design is done for a target output frequency of 1.2 GHz and the goal is to use it in a transmitter block of a high-speed serial link (HSSL). A thorough discussion of simulation results with phase noise and jitter results using circuit simulation tool follows the analysis.
Issue Date:2016-12
Genre:Other
Type:Text
Language:English
URI:http://hdl.handle.net/2142/97837
Date Available in IDEALS:2017-08-17


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