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Title:Implementing neural machine translator with bi-directional GRU and attention mechanism on FPGAS using HLS
Author(s):Li, Qin
Contributor(s):Chen, Deming
Subject(s):Machine Learning
Internet of Things
Abstract:Neural machine translation (NMT) is a popular topic in the natural language processing field. To further improve the accuracy of encoder-decoder based algorithms, an NMT model used bidirectional RNNs (Recurrent Neural Network), attention mechanism and beam search algorithm to improve the accuracy of the language translation. The implementation is realized in GPU because of its good performance on floating-point calculation and parallel programming. However, for obtaining better performance as well as lower power consumption, hardware implementation should be considered. In the NMT model, the large scope of its structure makes it hard for hardware implementation using purely RTL code. Therefore, we use Vivado High Level Synthesis tools to map the existing NMT model to a field-programmable gate array (FPGA) by using synthesizable C code and pragmas. The large Virtex UltraScale+ FPGA board is applied in this work to accommodate the large network flow. In our work, we build modules for the layers and algorithm applied in the NMT model, accelerate the computation inside each layer and utilize the hardware parallelism opportunity existing in the model. Both accelerating the computation and instantiating the same modules to satisfy parallelism lead to more resource usage, which is a good thing if resources are allocated efficiently. To make sure the resource in FPGA is enough for the entire flow, we develop a special structure for matrix multiplication to achieve both higher speed and less resource usage. In this case, the parallelized modules can be instantiated in limited utilities
Issue Date:2018-05
Date Available in IDEALS:2018-05-23

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