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oai:www.ideals.illinois.edu:2142/101228 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Chen, Deming Liu, Xinheng 2018-09-04T20:36:55Z 2018-09-04T20:36:55Z 2020-09-05T09:15:20Z 2018-04-25 2018-05 Targeting convolutional neural networks (CNNs), we adopt the high level synthesis (HLS) design methodology and explore various optimization and synthesis techniques to optimize design on an FPGA. Our motivation is to target embedded devices that operate as edge devices. Recently, as machine learning algorithms have become more practical, there have been much effort to implement them on devices that can be used in our daily lives. However, unlike server devices, edge devices are relatively small and thus have much more limited resources and performance. Therefore, control of resource usage and optimization play an important role when we want to implement machine learning algorithms on an edge device. The key idea explored in this thesis is backward pipeline scheduling which optimizes the pipeline between CNN layers. This optimization technique is especially useful to utilize the limited on-chip memory resource for classifying an image on an edge device. We have achieved latency of 175.7 μs for classifying one image in the MNIST data set using the LeNet and 653.5 μs for classifying one image in the Cifar-10 data set using the CifarNet. For the LeNet we were able to maintain high accuracy of 97.6% for the MNIST data set and 83.4% for the Cifar-10 data set. We achieved the best single-image latency, 5.2x faster for the LeNet and 1.95x faster for the CifarNet, compared with NVIDIA Jetson TX1. Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2020-05-01 The student, Xinheng Liu, accepted the attached license on 2018-04-25 at 16:17. The student, Xinheng Liu, submitted this Thesis for approval on 2018-04-25 at 16:32. This Thesis was approved for publication on 2018-04-25 at 16:58. DSpace SAF Submission Ingestion Package generated from Vireo submission #12495 on 2018-08-31 at 17:21:32 Made available in DSpace on 2018-09-04T20:36:55Z (GMT). No. of bitstreams: 2 LIU-THESIS-2018.pdf: 465564 bytes, checksum: ccd535e973d80355683d1fc3c84fdfaa (MD5) LICENSE.txt: 4208 bytes, checksum: 212ed2f4def6a3d45de6a15fda79959f (MD5) Previous issue date: 2018-04-25 Embargo set by: Seth Robbins for item 107312 Lift date: 2020-09-04T20:37:00Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 107312 Lift date: 2020-09-04T20:42:08Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only Restriction Lifted for Item 107312 on 2020-09-05T09:15:20Z. application/pdf http://hdl.handle.net/2142/101228 en © 2018 Xinheng Liu FPGA Convolutional Neural Network Optimization Acceleration High-Level Synthesis Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices text text M.S. Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis