2026-09-24T17:20:51Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/101358 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Embargo set by: Seth Robbins for item 107443 Lift date: 2020-09-04T20:50:11Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Open Restriction set for Item 107443 on 2019-05-09T15:52:26Z with date null by fschaef2@illinois.edu. Open Restriction set for Item 107443 on 2019-05-09T15:52:28Z with date null by fschaef2@illinois.edu. Open application/pdf http://hdl.handle.net/2142/101358 en Copyright 2018 Daniel Petrisko Kumar, Rakesh Petrisko, Daniel 2018-09-04T20:47:27Z 2018-09-04T20:47:27Z 2018-04-25 2018-05 Monolithic, single-die processors dominate today’s computing landscape. High performance systems achieve massive throughput by connecting large numbers of discrete chips – CPUs, GPUs, FPGAs – through high latency, low bandwidth interconnects. However, such systems provide limited performance scaling due to high communication costs between the discrete chips. This thesis proposes an alternate path for performance scaling: integrating many dies onto a single chip using a novel assembly technology – Silicon Interconnect Fabric (Si-IF). Many-die processors have both a technical and an economic advantage over their monolithic counterparts. We demonstrate potential benefits of a many-die approach using two approaches: efficient workload coverage design space exploration using many dies and evaluating a many-die wafer-scale GPU design. Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2020-05-01 The student, Daniel Petrisko, accepted the attached license on 2018-04-24 at 12:27. The student, Daniel Petrisko, submitted this Thesis for approval on 2018-04-24 at 12:41. This Thesis was approved for publication on 2018-04-25 at 08:30. DSpace SAF Submission Ingestion Package generated from Vireo submission #12382 on 2018-08-31 at 17:30:09 Made available in DSpace on 2018-09-04T20:47:27Z (GMT). No. of bitstreams: 3 PETRISKO-THESIS-2018.pdf: 1399726 bytes, checksum: 1be202642a7a10f0f4ee43925210502c (MD5) MSThesis.docx: 3984973 bytes, checksum: 9aa97f8afb8edbaf078ebb3591a8a360 (MD5) LICENSE.txt: 4212 bytes, checksum: cede8666af55e15ba53d91504aba8447 (MD5) Previous issue date: 2018-04-25 Embargo set by: Seth Robbins for item 107443 Lift date: 2020-09-04T20:47:38Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Computer Architecture Design Space Exploration Waferscale GPU Si-IF Architectural exploration of Si-IF many-die processors text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.