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oai:www.ideals.illinois.edu:2142/101631 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Rosenbaum, Elyse Mysore Vijayaraj, Prajwal 2018-09-27T16:18:05Z 2018-09-27T16:18:05Z 2018-07-20 2018-08 IEC-61000-4-2 compliant ESD discharges are performed on a microcontroller. The effect of ESD-induced noise on a digital system having a workload is examined. UART interface present on-chip is used for memory and register readout. Hardware voltage monitors developed previously are included in the design to report the on-die supply noise. A correlation between the voltage disturbance and soft errors induced is identified. The threshold for such disturbances is found. The results are validated across multiple chips. Memory elements are found to be more immune than registers. Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2018-09-27 without embargo terms The student, Prajwal Mysore Vijayaraj, accepted the attached license on 2018-07-20 at 15:49. The student, Prajwal Mysore Vijayaraj, submitted this Thesis for approval on 2018-07-20 at 16:33. This Thesis was approved for publication on 2018-07-20 at 16:39. DSpace SAF Submission Ingestion Package generated from Vireo submission #12954 on 2018-09-27 at 10:50:26 Made available in DSpace on 2018-09-27T16:18:05Z (GMT). No. of bitstreams: 2 MYSOREVIJAYARAJ-THESIS-2018.pdf: 9074256 bytes, checksum: ea711e9a984c72d5a0fb560911d80fb6 (MD5) LICENSE.txt: 4221 bytes, checksum: 9009b872a742cc839c2f7cfc8d173f12 (MD5) Previous issue date: 2018-07-20 application/pdf http://hdl.handle.net/2142/101631 en Copyright 2018 Prajwal Mysore Vijayaraj Bit flips ESD microcontroller soft errors Rail clamp Phase margin Detection of ESD-induced soft errors text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.