2026-09-20T11:46:25Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/101831 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Pilawa-Podgurski, Robert Ng, Pei Han 2018-09-27T16:47:36Z 2018-09-27T16:47:36Z 2020-09-28T09:15:16Z 2018-07-19 2018-08 The first on-chip three-level boost converter with 0.28 mm2 die size is implemented using 65 nm CMOS technology. Leveraging the advantages of hybrid switched capacitor converters, the converter manages to provide a maximum output voltage of 4.5 V with the available 2.5 V devices in this technology. The issue of capacitor imbalance, which has always been one of the factors that hinder high-efficiency power converters, is resolved by the hybrid current mode controller proposed in this work. The hardware implementation demonstrates that the capacitor converges to its balance voltage within 270 μs. A new level shifter circuitry is established in this thesis to mitigate the effect of asymmetrical gate signals by the level shifter. This delay-equalized level shifter is able to produce a symmetric delay less than 1 ns, allowing high-frequency phase-shifted switching operation in a hybrid switched capacitor (SC) converter. Together with both output voltage regulation and capacitor balancing, the converter operates efficiently up to 45 MHz for wide input range from 0.5 V to 3.0 V. This converter achieves a peak efficiency of 97.5% and peak output current of 83 mA. Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2020-08-01 The student, Pei Ng, accepted the attached license on 2018-07-19 at 11:34. The student, Pei Ng, submitted this Thesis for approval on 2018-07-19 at 11:45. This Thesis was approved for publication on 2018-07-19 at 11:59. DSpace SAF Submission Ingestion Package generated from Vireo submission #12937 on 2018-09-27 at 11:37:40 Made available in DSpace on 2018-09-27T16:47:36Z (GMT). No. of bitstreams: 13 NG-THESIS-2018.pdf: 6358697 bytes, checksum: b48312b1ba164d00100ed2eb97f7f6d3 (MD5) abs.tex: 1212 bytes, checksum: cd848a4ea22f84112000b7d6e97b7937 (MD5) ack.tex: 1299 bytes, checksum: d80fda94601795319a81fcb4e52c2e39 (MD5) background.tex: 12774 bytes, checksum: d6efe2298e55cd53cc62318255806958 (MD5) circuit.tex: 12829 bytes, checksum: 5ca7d55e6b9086b88709eb6c3ca56388 (MD5) concl.tex: 2593 bytes, checksum: eaad6b5c5a39684962eee313988d0ba9 (MD5) control.tex: 13454 bytes, checksum: 10ad8fe3b412e10cd32166b4cb86920c (MD5) ecethesis.tex: 5447 bytes, checksum: 625d34c3e3f6f12e9789ebdc52fcc545 (MD5) exper.tex: 19738 bytes, checksum: 918aed006c76bf94f49fad1b6c78417b (MD5) intro.tex: 7279 bytes, checksum: f70518efe678449cbc274401f7a2f00a (MD5) model.tex: 13561 bytes, checksum: 36a86b9d6f1421c96d8de62c9898f7e2 (MD5) sb.bib: 76670 bytes, checksum: da33f6ebcc14d91d43c63c4082d3fa40 (MD5) LICENSE.txt: 4203 bytes, checksum: 7141934100f6ba1adc67622c51211520 (MD5) Previous issue date: 2018-07-19 Embargo set by: Seth Robbins for item 107932 Lift date: 2020-09-27T16:47:41Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Limited Restriction Lifted for Item 107932 on 2020-09-28T09:15:16Z. application/pdf http://hdl.handle.net/2142/101831 en Copyright 2018 Pei Han Ng three-level boost converter hybrid switched capacitor (SC) current mode control delay-equalized level shifter capacitor balancing An on-chip three-level boost converter for energy harvesting application text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.