2026-09-20T23:51:19Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/104803 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Schutt-Ainé, José E. Rajwardan, Ashwarya 2019-08-23T19:51:46Z 2019-08-23T19:51:46Z 2019-04-11 2019-05 This thesis addresses the receiver equalization techniques for a 10 Gbps USB 3.1 link in 65 nm CMOS technology. Two types of equalizers are implemented: a continuous time linear equalizer (CTLE) and a 1-tap full-rate decision feedback equalizer (DFE). The combined CTLE and DFE architecture is simulated with an rms receiver clock jitter of 5.3 ps and achieves a BER < 10E−12 while consuming 3.3 mW at the Nyquist frequency of 5 GHz. Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2019-08-22 without embargo terms The student, Ashwarya Rajwardan, accepted the attached license on 2019-04-10 at 16:22. The student, Ashwarya Rajwardan, submitted this Thesis for approval on 2019-04-10 at 16:23. This Thesis was approved for publication on 2019-04-11 at 18:01. DSpace SAF Submission Ingestion Package generated from Vireo submission #13554 on 2019-08-22 at 14:42:29 Made available in DSpace on 2019-08-23T19:51:46Z (GMT). No. of bitstreams: 2 RAJWARDAN-THESIS-2019.pdf: 4259412 bytes, checksum: 9aaefb8b51bb26a57021a9f742cbd471 (MD5) LICENSE.txt: 4215 bytes, checksum: a8a488af3873770ceaa1d757ab0e5f4d (MD5) Previous issue date: 2019-04-11 application/pdf http://hdl.handle.net/2142/104803 en Copyright 2019 Ashwarya Rajwardan DFE, CTLE, Equalizer, Signal Integrity, High-speed serial link Receiver equalization for a 10 gigabit per second high-speed serial link in 65 nm CMOS technology text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.