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Huang, Jian Coats, Chance Christopher 2019-08-23T20:36:11Z 2019-08-23T20:36:11Z 2021-08-24T09:15:24Z 2019-04-25 2019-05 Recent advances in memory technology have led to the creation of high-performance, non-volatile alternatives to traditional DRAM, known as non-volatile memory (NVM). While this technology has provided immense opportunities to system designers, it has also presented new challenges since applications running on NVM systems require data persistence guarantees with respect to system crashes. To address this problem, many crash-consistency techniques, including logging and shadow paging, have been proposed. However, existing solutions can suffer from significant overheads on the critical path of execution or introduce extra write traffic to NVM, or even both. For instance, logging approaches introduce double writes for data and logs in the critical path of program execution, while shadow paging incurs significant write amplification and cache flushes to ensure durability. To provide persistence guarantees, this work proposes a transparent and efficient out-of-place update mechanism which provides atomic data durability without incurring a substantial number of additional writes or performance overheads. The key idea of the proposed approach is to write the updated data to a new location in NVM while keeping the old data unmodified until after the updated version becomes durable. To support out-of-place updates in NVM, this work introduces a lightweight and transparent persistence indirection layer, called PIL, along with minor changes to existing processor architectures which together enable efficient transaction execution in hardware. Experimental results with a variety of data structures and data-intensive applications show that PIL achieves low critical-path latency with small write amplification, which is close to that of a native system without persistence support. Compared with the state-of-the-art crash-consistency techniques, it improves application performance by up to 1.8× while reducing write amplification by up to 85.3%. PIL also demonstrates scalable data recovery capability on multi-core systems. Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2021-05-01 The student, Chance Coats, accepted the attached license on 2019-04-25 at 10:29. The student, Chance Coats, submitted this Thesis for approval on 2019-04-25 at 10:43. This Thesis was approved for publication on 2019-04-25 at 13:36. DSpace SAF Submission Ingestion Package generated from Vireo submission #13905 on 2019-08-22 at 15:08:36 Made available in DSpace on 2019-08-23T20:36:11Z (GMT). No. of bitstreams: 2 COATS-THESIS-2019.pdf: 1338713 bytes, checksum: 38d5429d7946617eb1606b12da9ce4a2 (MD5) LICENSE.txt: 4209 bytes, checksum: 59172eef1722a4681d16d97d62eba695 (MD5) Previous issue date: 2019-04-25 Embargo set by: Seth Robbins for item 112215 Lift date: 2021-08-23T20:36:18Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only Restriction Lifted for Item 112215 on 2021-08-24T09:15:24Z. application/pdf http://hdl.handle.net/2142/105096 en Copyright 2019 Chance Christopher Coats Non-volatile Memory NVM Persistence Memory Persistence Crash-consistency Reducing memory persistency overheads with transparent out-of-place updates text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.