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oai:www.ideals.illinois.edu:2142/106254 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Hanumolu, Pavan K. Yim, Chris 2020-03-02T21:58:26Z 2020-03-02T21:58:26Z 2019-12-09 2019-12 In a phase-locked loop (PLL), the phase-offset is a result from non-idealities that usually need to be minimized to reduce the reference spurs at the output. However, in certain applications such as multi-buses, we would like to control this offset so we can align the clock with the data. This thesis will explore the idea of controlling the phase-offset at the output of a charge-pump PLL (CPLL) by setting the current mismatch in the charge-pump module. Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2020-02-28 without embargo terms The student, Chris Yim, accepted the attached license on 2019-12-05 at 15:35. The student, Chris Yim, submitted this Thesis for approval on 2019-12-05 at 15:39. This Thesis was approved for publication on 2019-12-09 at 08:29. DSpace SAF Submission Ingestion Package generated from Vireo submission #14721 on 2020-02-28 at 17:15:51 Made available in DSpace on 2020-03-02T21:58:26Z (GMT). No. of bitstreams: 2 YIM-THESIS-2019.pdf: 2084202 bytes, checksum: f99f551b60861e81a4fd3373e8bf2230 (MD5) LICENSE.txt: 4206 bytes, checksum: d181b307401598372ce0a56d1f32cc76 (MD5) Previous issue date: 2019-12-09 application/pdf http://hdl.handle.net/2142/106254 en Copyright 2019 Chris Yim PLL CPLL charge-pump phase offset An integer-N charge-pump phase-locked loop with controllable phase offset text text Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.