2026-09-21T22:33:16Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/108436 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Kumar, Rakesh Cebry, Nicholas 2020-10-07T20:59:27Z 2020-10-07T20:59:27Z 2020-06-29 2020-08 Motivated by the failing of Moore’s law and Dennard scaling, as well as increasingly large parallel tasks like machine learning and big data analysis, processors continue to increase in area and incorporate more computational cores. This growth requires innovation in manufacturing processes to build larger systems, and architectural changes to enable performance to scale acceptably. One significant architectural change is the shift from bus and crossbar based processor interconnections to networks-on-chip (NoCs). This thesis details the design of an NoC to enable a shared memory architecture in a chiplet-based wafer scale processor with architectural support for up to 14,336 cores. Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2020-10-02 without embargo terms The student, Nicholas Cebry, accepted the attached license on 2020-06-29 at 11:25. The student, Nicholas Cebry, submitted this Thesis for approval on 2020-06-29 at 11:34. This Thesis was approved for publication on 2020-06-29 at 15:17. DSpace SAF Submission Ingestion Package generated from Vireo submission #15475 on 2020-10-02 at 15:10:41 Made available in DSpace on 2020-10-07T20:59:27Z (GMT). No. of bitstreams: 2 CEBRY-THESIS-2020.pdf: 1119986 bytes, checksum: 5367cdbcbad15c20a3f9cbfa220a9ffd (MD5) LICENSE.txt: 4211 bytes, checksum: 81c017e2375c8b26441deba336988228 (MD5) Previous issue date: 2020-06-29 application/pdf http://hdl.handle.net/2142/108436 en Copyright 2020 Nicholas Cebry network-on-chip waferscale Network-on-chip design for a chiplet-based waferscale processor text Thesis Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.