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oai:www.ideals.illinois.edu:2142/108557 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Hanumolu, Pavan Kumar Hanumolu, Pavan Kumar Banerjee, Arijit Schutt-Aine, Jose E Zhou, Jin Nandi, Timir 2020-10-07T22:07:09Z 2020-10-07T22:07:09Z 2022-10-07T22:44:53Z 2020-05-18 2020-08 Advances in CMOS technologies have brought benefits to both digital and analog integrated circuits. However, lower output impedance and reduced supply voltage have also caused newer challenges, especially for the design of operational amplifiers (op-amps) to implement gain. In this dissertation, dynamic/latch-based/regenerative amplifiers are explored where interrupted regeneration is used to implement the gain function. First, a 6-b current-domain interpolating pipelined flash analog-to-digital converter (ADC) is presented, where a novel current-shape-amplifier (CSA) based on a simple dynamic latch stage with interrupted regeneration is used to achieve 16 X interpolation factor using four interpolating stages. Thanks to this larger interpolation factor, ADC input capacitance is greatly reduced, which significantly eases the design of ADC driver circuits. The reduction in ADC throughput that accompanies classical interpolation methods is overcome by pipelining the proposed CSA-based interpolating stages. Fabricated in a 65 nm CMOS process, the prototype ADC consumes 43.8 mW at 1/1.25 V supply and achieves 26.8 dB signal-to-noise and distortion ratio (SNDR) and 35.2 dB spurious-free dynamic range (SFDR) at 4 GS/s with a 2 GHz input. Second, a study is conducted and a fully digital technique is proposed to calibrate the offset of interpolating flash ADCs. Compared to the state-of-the-art, this technique requires fewer comparators and needs fewer sets of input differential pairs. Offset cancellation is achieved by switching references (only during calibration) without extra loading at the input or the clock generator circuitry. The efficacy of this technique is demonstrated by simulating a 4 bit interpolating flash ADC which shows an effective number of bits (ENOB) improvement of 1.5 bits. Third, the non-idealities of the ADC are described and calibration techniques are proposed to improve the performance. Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2022-08-01 The student, Timir Nandi, accepted the attached license on 2020-05-14 at 15:51. The student, Timir Nandi, submitted this Dissertation for approval on 2020-05-14 at 16:08. This Dissertation was approved for publication on 2020-05-18 at 14:04. DSpace SAF Submission Ingestion Package generated from Vireo submission #15398 on 2020-10-02 at 15:30:38 Made available in DSpace on 2020-10-07T22:07:09Z (GMT). No. of bitstreams: 2 NANDI-DISSERTATION-2020.pdf: 6792002 bytes, checksum: 232e618735ee89d4bf1e506c19b5de53 (MD5) LICENSE.txt: 4208 bytes, checksum: 30983b06c485c6aaa468c7e06b569560 (MD5) Previous issue date: 2020-05-18 Embargo set by: Seth Robbins for item 116183 Lift date: 2022-10-07T22:07:19Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 116183 Lift date: 2022-10-07T22:44:53Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD system U of I Only application/pdf http://hdl.handle.net/2142/108557 en © 2020 Timir Nandi dynamic amplifier reset gain regeneration time interpolation pipelining latch flash ADC Dynamic amplifiers for analog-to-digital converters text Thesis Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Dissertation Ph.D.