2026-09-19T03:38:42Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/109602 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Li, Xiuling Yang, Zhendong 2021-03-05T21:45:37Z 2021-03-05T21:45:37Z 2023-03-05T21:47:41Z 2020-12-01 2020-12 This work reports a three-dimensional (3D) microwave L-C filter network enabled by a CMOS-compatible two-dimensional (2D) fabrication approach, which combines inductive (L) and capacitive (C) self-rolled-up membrane (S-RuM) components monolithically into a single L-C network structure, thereby greatly reducing the on-chip area footprint. The individual L-C elements are fabricated in-plane using standard semiconductor processing techniques, and subsequently triggered by the built-in stress to self-assemble and roll into cylindrical air-core architectures. By designing the planar structure geometry and constituent layer properties to achieve a specific number of turns with a desired inner diameter when the device is rolled up, the electrical characteristics can be engineered. The network layouts of the L and C components are also reconfigurable by selecting appropriate input, output, and ground contact routing topographies. The devices demonstrated here operate over the range of ~1-10 GHz. Their area and volume footprints are 0.095 mm2 and 0.01 mm3, respectively, which are ~10× smaller than most of the comparable conventional filter designs. These S-RuM-enabled 3D microtubular L-C filter networks represent a significant advancement for miniaturization and integration of RF devices for applications in mobile connectivity. Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2022-12-01 The student, Zhendong Yang, accepted the attached license on 2020-11-25 at 10:23. The student, Zhendong Yang, submitted this Thesis for approval on 2020-11-25 at 10:32. This Thesis was approved for publication on 2020-12-01 at 17:24. DSpace SAF Submission Ingestion Package generated from Vireo submission #15960 on 2021-03-04 at 16:32:27 Made available in DSpace on 2021-03-05T21:45:37Z (GMT). No. of bitstreams: 5 YANG-THESIS-2020.pdf: 1810386 bytes, checksum: 5e2b4bcb9dd2dff318b323b766ba2321 (MD5) Srum1_200X.mp4: 27888411 bytes, checksum: 8a5f4fab4134ef361e68dded454af8c2 (MD5) MS_Thesis V2.docx: 6437186 bytes, checksum: e0aabf2a40f516bb1047caa869547dac (MD5) Thesis Figures.pptx: 32904870 bytes, checksum: 9a9ee9c2e8bc74d996a81d86fe0b07a7 (MD5) LICENSE.txt: 4210 bytes, checksum: e538cfdfccdfbcc0183508254d380a0c (MD5) Previous issue date: 2020-12-01 Embargo set by: Seth Robbins for item 117307 Lift date: 2023-03-05T21:45:47Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Embargo set by: Seth Robbins for item 117307 Lift date: 2023-03-05T21:47:41Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD system Author requested closed access (OA after 2yrs) in Vireo ETD system Limited application/pdf http://hdl.handle.net/2142/109602 en Copyright 2020 Zhendong Yang Monolithic, rolled-up, MEMS, L-C network, Inductor, Capacitor Chip scale monolithic integration of inductive and capacitive components by self-rolled-up membrane nanotechnology text Thesis Electrical & Computer Eng Electrical & Computer Engr University of Illinois at Urbana-Champaign Thesis M.S.