2026-09-21T01:02:45Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/115759 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Schutt-Ainé, José E 2022-05 application/pdf en text Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01 The student, Qingyi Wang, accepted the attached license on 2022-04-29 at 15:10. The student, Qingyi Wang, submitted this Thesis for approval on 2022-04-29 at 15:13. This Thesis was approved for publication on 2022-04-29 at 15:22. DSpace SAF Submission Ingestion Package generated from Vireo submission #18017 on 2022-11-11 at 12:58:18 Stability analysis of voltage-in-current latency insertion method Wang, Qingyi 2022-04-29 Latency insertion methods Circuit simulation As the semiconductor industry produces more transistors with higher frequencies and a more compact chip design, the demand for a novel simulation tool capable of simulating large-scale circuits both quickly and accurately has been increasing. The latency insertion method (LIM) has been proposed as a viable alternative to the conventional SPICE simulator for the simulation of large networks as it enables linear numerical complexity and achieves significant speed improvement. In this thesis, an improved version of the LIM called the voltage-in-current latency insertion method (VinC LIM) is discussed. Special attention is devoted to the stability analysis of VinC LIM. We prove and demonstrate that VinC LIM overcomes the time step size limitation that the basic LIM faces and improves the stability significantly. With the larger time steps, VinC LIM can allow the simulation to finish in a much shorter time without suffering from the stability limitation. Thesis eng https://hdl.handle.net/2142/115759 Copyright 2022 Qingyi Wang M.S. Thesis Electrical & Computer Engr University of Illinois at Urbana-Champaign Electrical & Computer Eng