2026-09-22T00:45:24Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/116126 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Shanbhag, Naresh R 2022-08 application/pdf en text Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2024-08-01 The student, Han-Mo Ou, accepted the attached license on 2022-07-21 at 13:42. The student, Han-Mo Ou, submitted this Thesis for approval on 2022-07-21 at 15:06. This Thesis was approved for publication on 2022-07-21 at 16:31. DSpace SAF Submission Ingestion Package generated from Vireo submission #18399 on 2022-11-15 at 21:40:39 Signal processing methods to enhance the accuracy of MRAM-based in-memory architectures Ou, Han-Mo 2022-07-21 In-memory architectures MRAM Statistical compensation Digital signal processing In-memory computing for machine learning applications has drawn much interest from researchers since its inception in 2014. In-memory computing reduces delay and energy costs, the use of non-volatile memory increases storage density, and allows the processing of large data. One major challenge of in-memory architectures is to maintain high accuracy, since they employ analog computations and therefore suffer from noise and process variations as compared to their digital counterparts. Using in-memory computing for applications requiring high accuracy, such as digital signal processing, is therefore a major challenge. In this thesis, we discuss the impact of parasitic resistances in resistive memory-based in-memory architectures for matrix-vector multiplications. Parasitic wire resistances between memory cells, although small in value, have significant effects on the accuracy. This problem limits the ability to scale up the popular in-memory current-summing architectures. We employ a signal processing based-approach to the problem. A signal model of the in-memory bank is constructed from circuit analysis of the memory array and is subsequently used to employed to develop compensation methods. Our proposed activation scaling compensation achieves an 18 dB to 21 dB gain in signal-to-distortion ratio and is shown to substantially aid in-memory computing-based digital filtering. Activation scaling's low overhead (<0.01%) makes it suitable for on-chip implementation on future resistive memory-based designs. Thesis eng https://hdl.handle.net/2142/116126 Copyright 2022 Han-Mo Ou M.S. Thesis Electrical & Computer Engr University of Illinois at Urbana-Champaign Electrical & Computer Eng