2026-09-19T10:50:20Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/116129 2023-07-11 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Shanbhag, Naresh R 2022-08 application/pdf en text Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2024-08-01 The student, Michael Tuttle, accepted the attached license on 2022-07-21 at 01:46. The student, Michael Tuttle, submitted this Thesis for approval on 2022-07-21 at 02:08. This Thesis was approved for publication on 2022-07-21 at 16:57. DSpace SAF Submission Ingestion Package generated from Vireo submission #18404 on 2022-11-15 at 21:40:41 Efficient convolutional neural network inference on microcontrollers Tuttle, Michael 2022-07-21 Machine Learning TinyML Microcontrollers Convolutional neural networks CNN Pruning Convolutional Neural Networks provide state-of-the-art performance on a wide variety of computer vision tasks. However, the large size and computational complexity of these models makes their deployment on resource-constrained edge devices difficult. To remedy this, efficient versions of these layers such as depthwise-separable convolutions and sparse convolutions have been proposed which dramatically reduce the number of parameters and operations required for accurate inference. This work explores various optimizations for these layers on Cortex-M4 MCUs. Memory optimizations such as in-place DWS convolutions and patch-based inference reduce MobileNetV1 peak memory usage by $3.75\times$. The typically inefficient DW layers are sped up by $2\times$ over the CMSIS-NN reference kernel, and memory-aware sparsity enables up to $5.7\times$ speed-up over dense convolutional layers at $95\%$ sparsity. Thesis eng https://hdl.handle.net/2142/116129 Copyright 2022 Michael Tuttle M.S. Thesis Electrical & Computer Engr University of Illinois at Urbana-Champaign Electrical & Computer Eng