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        <identifier>oai:www.ideals.illinois.edu:2142/122005</identifier>
        <datestamp>2024-03-01</datestamp>
        <setSpec>col_2142_5131</setSpec>
        <setSpec>col_2142_8888</setSpec>
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        <thesis xmlns="http://www.ndltd.org/standards/metadata/etdms/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/" xsi:schemaLocation="http://www.ndltd.org/standards/metadata/etdms/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdms11.xsd http://purl.org/dc/elements/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdmsdc.xsd">
          <dc:contributor>Stillwell, Andrew R</dc:contributor>
          <dc:date>2023-12</dc:date>
          <dc:format>application/pdf</dc:format>
          <dc:language>en</dc:language>
          <dc:type>text</dc:type>
          <dc:description>Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2024-03-01 without embargo terms</dc:description>
          <dc:description>The student, Arjit Bali, accepted the attached license on 2023-11-20 at 17:32.</dc:description>
          <dc:description>The student, Arjit Bali, submitted this Thesis for approval on 2023-11-20 at 19:28.</dc:description>
          <dc:description>This Thesis was approved for publication on 2023-12-07 at 14:56.</dc:description>
          <dc:description>DSpace SAF Submission Ingestion Package generated from Vireo submission #19983 on 2024-03-01 at 13:14:52</dc:description>
          <dc:title>An interleaved multilevel inverter topology for high-frequency low-inductance motors</dc:title>
          <dc:creator>Bali, Arjit</dc:creator>
          <dc:subject>Multilevel Inverter</dc:subject>
          <dc:subject>Flying Capacitor Multilevel Converter</dc:subject>
          <dc:subject>Hybrid Active Neutral Point Clamped Converter</dc:subject>
          <dc:subject>Interleaved Hybrid Active Neutral Point Clamped Converter</dc:subject>
          <dc:subject>Dc-link Capacitor</dc:subject>
          <dc:subject>Interleaving</dc:subject>
          <dc:subject>Voltage Source Inverter</dc:subject>
          <dc:date>2023-12-07</dc:date>
          <dc:description>Electric vehicle and electric aviation applications require lightweight electro-mechanical energy conversion; however, passive components in the drive system can constrain the power density. Slotless machine construction can attain high power density, but such designs result in very low per-phase machine inductances. The reduced inductance imposes additional filtering requirements between the inverter and motor, which lower the power density benefits gained from the slotless design used. Furthermore, the dc-link capacitor within the inverter increases significantly the overall weight and volume. In this work, the advantages of interleaving multilevel topologies are discussed, and an interleaved hybrid active neutral point clamped (I-HANPC) converter is proposed to achieve reduced output filter sizes and enable a smaller dc-link capacitor. The design is demonstrated with a 7-level I-HANPC experimental hardware prototype that attains a peak efficiency of 98.8% with low output total harmonic distortion.</dc:description>
          <dc:type>Text</dc:type>
          <dc:language>eng</dc:language>
          <dc:identifier>https://hdl.handle.net/2142/122005</dc:identifier>
          <dc:rights>Copyright 2023 Arjit Bali</dc:rights>
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            <name>M.S.</name>
            <level>Thesis</level>
            <discipline>Electrical &amp; Computer Engr</discipline>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
            <department>Electrical &amp; Computer Eng</department>
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