2026-09-22T14:16:06Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/124373 2024-09-16 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Schutt-Ainé, José E 2024-05 application/pdf en text Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2024-09-16 without embargo terms The student, Qiuyu Wang, accepted the attached license on 2024-04-22 at 19:04. The student, Qiuyu Wang, submitted this Thesis for approval on 2024-04-22 at 19:18. This Thesis was approved for publication on 2024-04-30 at 13:51. DSpace SAF Submission Ingestion Package generated from Vireo submission #20558 on 2024-09-16 at 00:35:50 2024-04-30 Phase-locked Loop Pll Mixed-signal Ic Design High-speed Link This thesis presents readers, especially undergraduate electrical engineering students in their junior or senior years who have solid background knowledge in Integrated Circuits (IC) design and strong passion in the semiconductor industry, with some flavors of the fundamentals of the mixed-signal IC design of a phase-locked loop (PLL) implemented in 180nm technology node and operated at a center frequency of 1.28GHz. It begins by introducing the applications and motivations of PLLs. The thesis then moves on by diving deep into the discussion of each of the PLL component’s intuition, schematic, characteristic, and linear model. Afterwards, a complete analysis of PLL is conducted, including its block diagram, linear model, stability, and characteristics, etc. The thesis finishes with the conclusion and discussion of future work to improve the PLL design. Text eng https://hdl.handle.net/2142/124373 © 2024 Qiuyu Wang Design and analysis of a 1.28ghz charge pump phase-locked loop in 180nm technology node Wang, Qiuyu M.S. Thesis Electrical & Computer Engr University of Illinois at Urbana-Champaign Electrical & Computer Eng