2026-09-22T00:22:25Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/124532 2026-01-14 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Rosenbaum, Elyse 2024-05 application/pdf en text Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01 The student, Ram Krishna, accepted the attached license on 2024-04-15 at 20:21. The student, Ram Krishna, submitted this Thesis for approval on 2024-04-15 at 20:21. This Thesis was approved for publication on 2024-04-21 at 17:19. DSpace SAF Submission Ingestion Package generated from Vireo submission #20425 on 2024-09-16 at 00:43:44 Power and signal delivery networks for heterogeneously integrated chiplets Krishna, Ram 2024-04-21 Chiplet Pdn Bow It is increasingly challenging to satisfy the requirements placed on the power delivery network for a multilevel hierarchical system, due to aggressive voltage scaling and stringent limits on the chip-level voltage droop. This thesis presents a methodology to obtain the minimum number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupling capacitors to meet a user-specified target impedance. The number and location optimizations are performed using nature-based and Bayesian optimization algorithms along with the quantitative comparison of results. This thesis also advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and simulation of signal and power integrity of Bunch-of-Wires (BoW) based die-to-die interconnects with advanced packaging technology. The study covers data rates up to 16 Gbps and includes a circuit-level implementation of the BoW slice consisting of a driver on one chiplet and a receiver on another chiplet. The width, spacing, and length of the high-density transmission lines are treated as variables in this work, and BoW data line configurations with extremely low power dissipation, less than 0.2 pJ/bit at 8 and 16 Gbps, are identified. Text eng https://hdl.handle.net/2142/124532 Copyright 2024 Ram Krishna M.S. Thesis Electrical & Computer Engr University of Illinois at Urbana-Champaign Electrical & Computer Eng