2026-09-22T06:03:56Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/129479 2026-02-05 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

application/pdf en text Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-05-01 The student, Yuanqi Guo, accepted the attached license on 2025-01-06 at 15:47. The student, Yuanqi Guo, submitted this Thesis for approval on 2025-01-06 at 16:01. This Thesis was approved for publication on 2025-01-13 at 13:46. DSpace SAF Submission Ingestion Package generated from Vireo submission #21251 on 2025-10-19 at 19:13:45 ESD robustness of stacked NMOS transistors for high-voltage tolerant output drivers in FinFET technology Guo, Yuanqi 2025-01-13 Rosenbaum, Elyse ESD Stacked NMOS high-voltage tolerant output drivers CDM VF-TLP eng This thesis describes a study designed to enhance the understanding of the reliability of doubly-stacked NMOS transistors under Charged Device Model (CDM) electrostatic discharge (ESD) conditions. Stacked NMOS are commonly used in high-voltage tolerant output drivers. The transistors used for this study are fabricated in a FinFET CMOS process. The test structures were designed such that the robustness of doubly-stacked NMOS devices could be evaluated as a function of the applied gate bias and the layout style. Very-Fast Transmission Line Pulse (VF TLP) measurements were used to evaluate the ESD robustness and the dynamic response. Based on the experimental results and subsequent analysis, design recommendations and a biasing strategy for cascoded output drivers are proposed. The objective is to improve the ESD reliability of high-voltage tolerant output drivers. 2025-05 Thesis https://hdl.handle.net/2142/129479 Copyright 2025 Yuanqi Guo Electrical & Computer Eng Electrical & Computer Engr University of Illinois Urbana-Champaign M.S. Thesis