2026-09-20T15:34:19Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/129760 2026-02-05 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

application/pdf en text Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01 The student, Hanchen Ye, accepted the attached license on 2025-05-01 at 12:56. The student, Hanchen Ye, submitted this Dissertation for approval on 2025-05-01 at 13:32. This Dissertation was approved for publication on 2025-05-01 at 14:30. DSpace SAF Submission Ingestion Package generated from Vireo submission #22119 on 2025-10-19 at 19:54:49 Scalable High-Level Synthesis for AI accelerator design Ye, Hanchen 2025-05-01 Chen, Deming Chen, Deming Adve, Vikram Huang, Jian Neuendorffer, Stephen High-Level Synthesis (HLS) AI Accelerator FPGA ASIC Design Space Exploration (DSE) Deep Neural Networks (DNNs) Compiler Dataflow Intermediate Representation (IR) MLIR Electronic Design Automation (EDA) Hardware-Software Co-design Large Language Models (LLMs) Convolutional Neural Networks (CNNs) eng The growing scale and complexity of deep neural networks (DNNs) present significant challenges for efficient hardware acceleration. High-Level Synthesis (HLS) has emerged as a promising methodology to enhance design productivity for FPGA- and ASIC-based accelerators. However, existing HLS workflows struggle to scale effectively due to their inability to address cross-stack co-design challenges spanning architecture design, compiler infrastructure, and Electronic Design Automation (EDA) algorithms. This dissertation proposes a comprehensive and scalable HLS methodology for AI accelerator design by innovating across three synergistic levels. At the design level, we present HybridDNN and DNNExplorer, two frameworks that facilitate the generation and exploration of hardware accelerators through algorithm-aware modeling and fine-grained design space exploration. At the compiler level, we develop ScaleHLS, HIDA, and StreamTensor, which together form a scalable HLS compiler stack that supports multi-level intermediate representations, design space optimizations, and hardware-aware scheduling for both generic and dataflow-based accelerators. At the EDA level, we introduce ISDC, an iterative scheduling algorithm that integrates feedback from downstream tools to significantly enhance resource utilization. Collectively, these contributions constitute a full-stack solution to scalable HLS, advancing the productivity, performance, and adaptability of AI accelerator design. 2025-05 Thesis https://hdl.handle.net/2142/129760 Copyright 2025 Hanchen Ye Electrical & Computer Eng Electrical & Computer Engr University of Illinois Urbana-Champaign Ph.D. Dissertation