2026-09-19T21:10:59Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/129780 2026-02-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

application/pdf en text Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01 The student, Ji Shi, accepted the attached license on 2025-05-06 at 17:01. The student, Ji Shi, submitted this Thesis for approval on 2025-05-06 at 17:06. This Thesis was approved for publication on 2025-05-07 at 14:02. DSpace SAF Submission Ingestion Package generated from Vireo submission #22239 on 2025-10-19 at 19:55:45 High-swing PAM4 electrical transmitter with clock data recovery based timing error correction Shi, Ji 2025-05-07 Hanumolu, Pavan Kumar High Speed Wireline Ic Clock Correction Serdes eng This thesis presents a high-swing PAM4 transmitter with an integrated CDR based timing calibration architecture implemented in a 16nm CMOS process. The proposed transmitter achieves a differential output swing of 2VDD using standard core devices. A CDR-based timing calibration circuit is introduced that detects timing errors at the transmitter output, allowing correction of all timing non-idealities throughout the signal path. Simulation results demon strate improved eye quality after calibration for PAM4 signaling. 2025-05 Text https://hdl.handle.net/2142/129780 Copyright 2025 Ji Shi Electrical & Computer Eng Electrical & Computer Engr University of Illinois Urbana-Champaign M.S. Thesis