2026-09-23T05:01:47Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/132461 2026-02-20 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

application/pdf en text Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2026-02-19 without embargo terms The student, Patrick Sear, accepted the attached license on 2025-09-03 at 14:43. The student, Patrick Sear, submitted this Thesis for approval on 2025-09-03 at 14:48. This Thesis was approved for publication on 2025-09-22 at 15:48. DSpace SAF Submission Ingestion Package generated from Vireo submission #22788 on 2026-02-19 at 18:24:14 Victim structures for predicting the ESD reliability of IO circuits Sear, Patrick 2025-09-22 Rosenbaum, Elyse ESD Circuit Design eng Compact, wafer-level ESD victim circuits that fail similarly to real IO circuits are used to validate the performance of ESD protection schemes in a 65-nm process technology. Electrical failure analysis identifies the device that fails during the ESD testing. Effects of circuit topologies and victim design choices on measured failure level are evaluated, and a follow-up chip is designed to extend the testing capability to CDM. The measured response of victim circuits is utilized to validate ESD compact models. Compact models are used to investigate the prediction of device failure in simulation. 2025-12 Thesis https://hdl.handle.net/2142/132461 Copyright 2025 Patrick Sear Electrical & Computer Eng Electrical & Computer Engr University of Illinois Urbana-Champaign M.S. Thesis