2026-09-21T12:51:16Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/132607 2026-02-20 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

application/pdf en text Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2026-02-19 without embargo terms The student, John Burns, accepted the attached license on 2025-12-12 at 11:47. The student, John Burns, submitted this Thesis for approval on 2025-12-12 at 11:56. This Thesis was approved for publication on 2025-12-12 at 13:07. DSpace SAF Submission Ingestion Package generated from Vireo submission #23150 on 2026-02-19 at 18:30:36 A 1.7GS/s SAR ADC in 28nm CMOS Burns, John Erick 2025-12-12 Hanumolu, Pavan K SAR ADC Pipelined SAR ADC Passive residue transfer Partial interleaving eng This thesis presents a 1.7GS/s 9b single channel SAR ADC in 28nm CMOS technology. The main focus of the thesis is the leveraging of the pipelining, passive residue transfer, and partial interleaving techniques to increase sample rate of the ADC. The first chapter explains the motivation for increasing the single channel ADC speed as well as the operation of the SAR ADC and pipelined SAR ADC and their inherent limitations. The second chapter presents the architecture investigated in this project. The third chapter details the circuit level implementation of the ADC. The fourth chapter shows simulation results, and the fifth chapter presents the conclusions. 2025-12 Thesis https://hdl.handle.net/2142/132607 Copyright 2025 John Burns Electrical & Computer Eng Electrical & Computer Engr University of Illinois Urbana-Champaign M.S. Thesis