2026-09-19T02:39:12Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/132701 2026-03-24 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

application/pdf en text Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2027-12-01 The student, Yang Zhou, accepted the attached license on 2025-12-09 at 08:37. The student, Yang Zhou, submitted this Thesis for approval on 2025-12-09 at 08:50. This Thesis was approved for publication on 2025-12-09 at 13:51. DSpace SAF Submission Ingestion Package generated from Vireo submission #23110 on 2026-02-19 at 18:46:53 Demystifying CXL type-2 devices—with composable CXL-SSDS as a case study Zhou, Yang 2025-12-09 Kim, Nam Sung Compute Express Link Heterogeneous Computing eng CXL is a PCIe-based interconnect that defines three protocols for three classes of devices, each with distinct capabilities. Commercial adoption has arrived first for CXL Type-3 devices, with CXL Type-2 devices emerging afterward—making it timely to clarify CXL Type-2 device’s capabilities and applications. We first examine three core CXL Type-2 device features: cache-coherent device accelerator to host memory, device accelerator to device memory, and host CPU to device memory accesses. We then introduce CXL-AnySSD, a composable, memory-semantic CXL-SSD that exploits hardware-managed device-to-host transfers in CXL Type-2 devices. By loosely coupling DRAM with commodity SSDs, CXL-AnySSD decouples capacity from performance, supports heterogeneous SSD choices, and removes OS-managed swap overheads. We implement a CXL-AnySSD prototype on a real CXL Type-2 device and show CXL-AnySSD improves end-to-end throughput by 2.3–6.2× over OS-managed SSD swap on a vector-database workload. 2025-12 Thesis https://hdl.handle.net/2142/132701 Copyright 2025 Yang Zhou Electrical & Computer Eng Electrical & Computer Engr University of Illinois Urbana-Champaign M.S. Thesis