2026-09-21T10:04:03Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/132810 2026-03-24 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

application/pdf en text Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01 The student, Shuozhen Liu, accepted the attached license on 2025-12-11 at 12:41. The student, Shuozhen Liu, submitted this Thesis for approval on 2025-12-11 at 12:55. This Thesis was approved for publication on 2025-12-12 at 11:06. DSpace SAF Submission Ingestion Package generated from Vireo submission #23119 on 2026-02-19 at 20:10:10 Design of residue amplifiers for high-speed pipelined-SAR ADCs Liu, Shuozhen 2025-12-12 Hanumolu, Pavan K. Analog-to-digital converter (ADC), Residue Amplifiers (RA), pipelined successive approximate register (SAR) eng This thesis presents the design of a high-speed Gm-R residue amplifier used in a pipelined-SAR ADC, implemented in a 28nm CMOS process. The proposed design achieves good linearity and low gain variation due to temperature using a constant-gm biasing network. The thesis is organized as follows: Chapter 1 introduces the concepts of ADCs and residue amplification. Chapter 2 discusses the backgrounds on architecture of the SAR ADC and pipelined-SAR ADC, and introduces residue amplifier design for pipelined-SAR ADC. Chapter 3 introduces the ADC architecture that is used with the Gm-R residue amplifier, design process and considerations of the Gm-R residue amplifier and layout. Chapter 4 shows the simulation results for the residue amplifier gain and nonlinearity, along with the ADC system level performances. Chapter 5 summarizes the findings and concludes the thesis. 2025-12 Thesis https://hdl.handle.net/2142/132810 Copyright 2025 Shuozhen Liu Electrical & Computer Eng Electrical & Computer Engr University of Illinois Urbana-Champaign M.S. Thesis