2026-09-22T02:46:07Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/132812 2026-03-24 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

application/pdf en text Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-12-01 The student, Zetai Liu, accepted the attached license on 2025-12-10 at 14:12. The student, Zetai Liu, submitted this Thesis for approval on 2025-12-10 at 14:19. This Thesis was approved for publication on 2025-12-10 at 19:08. DSpace SAF Submission Ingestion Package generated from Vireo submission #23126 on 2026-02-19 at 20:10:10 Development of electrical and optical devices for next generation high-speed optical interconnects Liu, Zetai 2025-12-10 Feng, Milton High Speed Data Com, VCSEL, HBT, Fabrication, Testing eng Rapid advances in AI, LLMs, and IoT are pushing data traffic toward >1.6 Tb/s optical links with much lower energy per bit. VCSEL based multichannel transceivers are one of the most cost- and power-efficient choice for short-reach interconnects, but further scaling is limited by modal dispersion in multimode VCSELs and bandwidth/power ceilings in both VCSELs and silicon driver/control ICs as per-lane rates exceed 200 Gb/s. Accordingly, overcoming optical limitations requires both aggressive aperture scale-down and targeted process advancements in VCSEL fabrication. The electrical limits motivate using higher-speed electronic devices such as InP based Type-II DHBTs. Meanwhile, cryogenic and quantum computing demand ultra-efficient links bridging cryogenic processors to room-temperature peripheral electronics; Cryo-VCSELs offer ~100 GHz bandwidth at few milliampere bias range and enable >448-Gb/s PAM-4 operation but require tighter process control and microcavity-scaling insight. This thesis advances two fronts: first, a wafer-scale, OpenCV-based automated oxide-aperture measurement method that replaces manual ImageJ, enabling full-wafer oxidation maps at high throughput and exposing critical nonuniformities for <3-µm apertures; and, second, a quantitative study of emitter-ledge effects in sub-micron InP/GaAsSb Type-II DHBTs, showing a 160-nm ledge can more than double DC current gain β by suppressing surface recombination, but with trade-offs in ideality factor, yield, base resistance, and fT/fmax. Together, these results provide the process capability and device understanding needed to co-optimize Cryo-VCSEL sources and InP-DHBT electronics for fJ/bit-class, long-reach optical interconnects in hybrid-temperature computing systems. 2025-12 Thesis https://hdl.handle.net/2142/132812 Copyright 2025 Zetai Liu Electrical & Computer Eng Electrical & Computer Engr University of Illinois Urbana-Champaign M.S. Thesis