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oai:www.ideals.illinois.edu:2142/14617 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Torrellas, Josep Torrellas, Josep Karpuzcu, Rahmet U. 2010-01-06T16:19:48Z 2010-01-06T16:19:48Z 2010-01-06T16:19:48Z Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly increasing with technology scaling. In future designs, the majority of the cores will necessarily have to be dormant at any given time to meet the power budget. To push back the many-core power wall, this work introduces Dynamic Voltage Scaling for Aging Management (DVSAM) — a new scheme for trading off processor aging for performance and power. DVSAM can be used to maximize performance, minimize power, or boost performance for a short life. In addition, this work introduces the BubbleWrap many-core, an architecture that makes use of DVSAM. BubbleWrap identifies the most power-efficient cores on a variation-affected chip and designates them as Throughput cores dedicated to parallel-section execution; the rest of the cores (Expendable cores) are dedicated to sequential sections. In one use of DVSAM, BubbleWrap sacrifices Expendable cores one at a time by running them at elevated V dd for a month or so each, until they completely wear out. Our simulations show that a 32-core BubbleWrap many-core provides substantial improvements over a plain chip. For example, on average, one design runs fully sequential applications at a 22% higher frequency, and fully parallel applications with a 33% higher throughput. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2009-10-23T15:23:30Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 karpuzcu_rahmet.pdf: 1686314 bytes, checksum: 6035d4f6073df72a5d90a4b37c8a6d30 (MD5) Made available in DSpace on 2010-01-06T16:19:48Z (GMT). No. of bitstreams: 2 license.txt: 4064 bytes, checksum: 8f810425b21d6ef27d5492884c53a5a8 (MD5) karpuzcu_rahmet.pdf: 1686314 bytes, checksum: 6035d4f6073df72a5d90a4b37c8a6d30 (MD5) http://hdl.handle.net/2142/14617 en @ 2009 Rahmet Ulya Karpuzcu Processor Aging Voltage Scaling Process Scaling Power Wall. Managing Many-Core Aging 2009-12 Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. PHD:Electr & Computer Eng-UIUC 10KS1200PHD