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        <identifier>oai:www.ideals.illinois.edu:2142/14658</identifier>
        <datestamp>2023-07-10</datestamp>
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        <thesis xmlns="http://www.ndltd.org/standards/metadata/etdms/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/" xsi:schemaLocation="http://www.ndltd.org/standards/metadata/etdms/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdms11.xsd http://purl.org/dc/elements/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdmsdc.xsd">
          <dc:contributor>Borisov, Nikita</dc:contributor>
          <dc:contributor>Borisov, Nikita</dc:contributor>
          <dc:creator>Albrecht, David R.</dc:creator>
          <dc:date>2010-01-06T16:20:41Z</dc:date>
          <dc:date>2010-01-06T16:20:41Z</dc:date>
          <dc:date>2010-01-06T16:20:41Z</dc:date>
          <dc:description>Fast data rates and complicated protocols have outpaced network intrusion detection systems. Administrators are forced to choose between breadth and depth: systems either deeply analyze traﬃc for a small handful of vulnerabilities, or search for many in parallel using more primitive (and easily evadable) techniques. We present a new parser architecture called VESPA, which uses the concept of vulnerability signatures to oﬀer both speed and accuracy. VESPA is informed by a study of network protocols, which precedes the design. We conclude by reviewing several trends in 
computer architecture, and their impact on future intrusion detection systems. We believe a system which oﬀers both speed and accuracy is 
possible, but requires rethinking how network intrusion detectors are designed, in light of trends in computer architecture.</dc:description>
          <dc:description>Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2009-12-08T22:32:24Z
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          <dc:identifier>http://hdl.handle.net/2142/14658</dc:identifier>
          <dc:language>en</dc:language>
          <dc:rights>Copyright 2009 David Albrecht.</dc:rights>
          <dc:subject>intrusion detection</dc:subject>
          <dc:subject>computer architecture</dc:subject>
          <dc:subject>multicore</dc:subject>
          <dc:subject>stream processing</dc:subject>
          <dc:subject>click</dc:subject>
          <dc:subject>bro</dc:subject>
          <dc:subject>vespa</dc:subject>
          <dc:subject>parallelism</dc:subject>
          <dc:title>High Performance Network Intrusion Detection: A New Paradigm is Needed</dc:title>
          <dc:date>2009-12</dc:date>
          <degree>
            <department>Electrical &amp; Computer Eng</department>
            <departmentCode>1933</departmentCode>
            <discipline>Electrical &amp; Computer Engr</discipline>
            <disciplineCode>1200</disciplineCode>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
            <level>Thesis</level>
            <name>M.S.</name>
            <program>MS:Electr &amp; Computer Eng-UIUC</program>
            <programCode>10KS1200MS</programCode>
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