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oai:www.ideals.illinois.edu:2142/16224 2023-07-10 col_2142_8888 col_2142_5131 com_2142_8887 com_2142_234 com_2142_5130

Caccamo, Marco Chivukula, Deepti K. 2010-05-19T18:41:07Z 2010-05-19T18:41:07Z 2010-05-19T18:41:07Z 2010-5 Real-time computing is the study of hardware and software systems that are subject to a “real-time constraint” - i.e., strict deadline guarantees. With uncontrollable cache and front side bus, in the modern computer architectures, the estimation of a tight bound, worst case execution time (WCET) is difficult. The new generation computer architecture, Cell Broadband Engine Architecture (CBEA), has a software controlled front side bus (i.e. Element Interconnect Bus) that helps moderate the unpredictable task execution time problem. The CBEA is a heterogeneous chip system containing one Power Processing Element (PPE) and eight Synergistic Processing Elements (SPEs), each having an internal independent local storage memory. In this thesis, using CBEA as a platform, I implemented an interrupt based scheduling framework that uses Element Interconnect Bus (EIB) in a temporally predictable manner. The framework is built by abstracting away low-level architectural features. Experiments were also performed to show that the real-time transactions of feasible transaction sets are executed before deadline when scheduled according to a real-time scheduling algorithm, while the same transactions can miss their deadlines when scheduled according to an arbitrary (non-real-time) scheduling policy. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-04-02T21:43:40Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Chivukula_Deepti.rar: 3039446 bytes, checksum: 281420c56835d762e415c8d85370b11a (MD5) Chivukula_Deepti.pdf: 917205 bytes, checksum: 061f5c9443ab3b41b87d7000c88a50ce (MD5) Made available in DSpace on 2010-05-19T18:41:07Z (GMT). No. of bitstreams: 3 Chivukula_Deepti.rar: 3039446 bytes, checksum: 281420c56835d762e415c8d85370b11a (MD5) Chivukula_Deepti.pdf: 917205 bytes, checksum: 061f5c9443ab3b41b87d7000c88a50ce (MD5) license.txt: 4066 bytes, checksum: 2c644c2b9061b0de1f2969b8bad7c71e (MD5) http://hdl.handle.net/2142/16224 en Copyright 2010 Deepti Kumar Chivukula Bus Scheduling Cell Processor Bus scheduling implementation on the cell processor Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. MS:Electr & Computer Eng-UIUC 10KS1200MS