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        <identifier>oai:www.ideals.illinois.edu:2142/16472</identifier>
        <datestamp>2023-07-10</datestamp>
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        <thesis xmlns="http://www.ndltd.org/standards/metadata/etdms/1.1/" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:dc="http://purl.org/dc/elements/1.1/" xsi:schemaLocation="http://www.ndltd.org/standards/metadata/etdms/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdms11.xsd http://purl.org/dc/elements/1.1/ http://www.ndltd.org/standards/metadata/etdms/1.1/etdmsdc.xsd">
          <dc:contributor>Patel, Sanjay J.</dc:contributor>
          <dc:creator>Truty, Wojciech J.</dc:creator>
          <dc:date>2010-06-22T19:37:13Z</dc:date>
          <dc:date>2010-06-22T19:37:13Z</dc:date>
          <dc:date>2010-06-22T19:37:13Z</dc:date>
          <dc:description>Scientific applications rely heavily on floating point data types. Floating point operations
are complex and require complicated hardware that is both area and power intensive. The
emergence of massively parallel architectures like Rigel creates new challenges and poses new
questions with respect to 
floating point support. The massively parallel aspect of Rigel places great emphasis on area efficient, low power designs. At the same time, Rigel is a general
purpose accelerator and must provide high performance for a wide class of applications. This
thesis presents an analysis of various floating point unit (FPU) components with respect to
Rigel, and attempts to present a candidate design of an FPU that balances performance,
area, and power and is suitable for massively parallel architectures like Rigel.</dc:description>
          <dc:description>Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-04-07T18:03:24Z
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          <dc:identifier>http://hdl.handle.net/2142/16472</dc:identifier>
          <dc:language>en</dc:language>
          <dc:rights>Copyright 2010 Wojciech Truty</dc:rights>
          <dc:subject>Floating point</dc:subject>
          <dc:subject>Rigel</dc:subject>
          <dc:subject>parallel</dc:subject>
          <dc:subject>many core</dc:subject>
          <dc:subject>multicore</dc:subject>
          <dc:subject>processor</dc:subject>
          <dc:subject>Accelerator</dc:subject>
          <dc:subject>Floating point unit (FPU)</dc:subject>
          <dc:subject>floating point unit</dc:subject>
          <dc:subject>IEEE Standard for Floating-Point Arithmetic (IEEE 754)</dc:subject>
          <dc:subject>Massively parallel</dc:subject>
          <dc:title>Design and implementation of a floating point unit for rigel, a massively parallel accelerator</dc:title>
          <degree>
            <department>Electrical &amp; Computer Engineering</department>
            <departmentCode>1933</departmentCode>
            <discipline>Electrical &amp; Computer Engineering</discipline>
            <disciplineCode>1200</disciplineCode>
            <grantor>University of Illinois at Urbana-Champaign</grantor>
            <level>Thesis</level>
            <name>M.S.</name>
            <program>MS:Electr &amp; Computer Eng-UIUC</program>
            <programCode>10KS1200MS</programCode>
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