2026-09-19T20:01:59Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/18286 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Kumar, Rakesh Sartori, John M. 2011-01-14T22:44:50Z 2011-01-14T22:44:50Z 2011-01-14T22:44:50Z Conventional CAD methodologies optimize a processor module for correct operation and prohibit timing violations during nominal operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate instead of correct operation. The target error rate is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power bene ts are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a design-level methodology that minimizes the power of a processor module for a target error rate. We show how this design-level methodology can be extended to design recovery-driven processors -- processors that are optimized to take advantage of hardware or software error resilience. These may be single-core processors or heterogeneously-reliable multi-core processors, in which individual cores are optimized for different reliability targets. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of error rates to create soft processors -- processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of error rates. We demonstrate significant power benefits over conventional design -- 11.8% on average over all modules and error rate targets, and up to 29.1% for individual modules. Processor- level benefits are 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases. Item withdrawn by Mark Zulauf (zulauf@illinois.edu) on 2010-11-17T22:53:24Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 Sartori_John.zip: 58340 bytes, checksum: 224d20f89d6e987c3c2431bc14d8c949 (MD5) Sartori_John.pdf: 1837751 bytes, checksum: 6b0fd9b4f70ce4fc96bf0e0b6f8d9cb5 (MD5) Made available in DSpace on 2011-01-14T22:44:50Z (GMT). No. of bitstreams: 3 Sartori_John.pdf: 1837751 bytes, checksum: 6b0fd9b4f70ce4fc96bf0e0b6f8d9cb5 (MD5) license.txt: 4062 bytes, checksum: d253262ffb3e60878716b458a3d69ea4 (MD5) Sartori_John.zip: 58340 bytes, checksum: 224d20f89d6e987c3c2431bc14d8c949 (MD5) http://hdl.handle.net/2142/18286 en Copyright 2010 John M. Sartori recovery-driven design energy efficiency error resilience Recovery-driven design: Exploiting error resilience in design of energy-efficient processors 2010-12 Electrical & Computer Eng 1933 Electrical & Computer Engr 1200 University of Illinois at Urbana-Champaign Thesis M.S. PHD:Electr & Computer Eng-UIUC 10KS1200PHD