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Saleh, Resve A. Yang, Fred Lei 2011-05-07T12:03:22Z 2011-05-07T12:03:22Z 10000-01-01 1992 The purpose of this research is to develop effective simulation methods for electrically oriented faults in digital metal-oxide semiconductor (MOS) very large scale integrated (VLSI) circuits. In particular, we are interested in the simulation of permanent electrical faults that are difficult to model using a logic-level or switch-level simulator, and the simulation of transient faults that have a time-varying characteristic during the simulation. The simulation of these types of faults is inherently expensive because it requires detailed circuit-level analysis due to their electrical nature. These problems are addressed using mixed-mode simulation techniques in which the fault-free portions of the circuit are simulated using logic-level simulation techniques while the faulty portions of the circuit are simulated using electrical-level simulation techniques. In addition, since transient faults manifest their electrical nature only for a very short period of time, a dynamic mixed-mode simulation technique is developed to take advantage of this property to speed up further the simulation of transient faults. These algorithms have been implemented in the programs F/SPLICE3 and DYNAMO with significant improvements in simulation speed compared to those for previous approaches. Made available in DSpace on 2011-05-07T12:03:22Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9305740.pdf: 4269008 bytes, checksum: 89a4dbef460b2e31e350e52b75047285 (MD5) Previous issue date: 1992 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:36:03Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:14:27-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9305740 (UMI)AAI9305740 http://hdl.handle.net/2142/19306 eng Copyright 1992 Yang, Fred Lei Engineering, Electronics and Electrical Simulation of faults causing analog behavior in digital circuits text Dissertation Ph.D. Electrical and Computer Engineering Electrical Engineering University of Illinois at Urbana-Champaign