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oai:www.ideals.illinois.edu:2142/19412 2023-07-10 col_2142_5131 col_2142_8888 com_2142_5130 com_2142_8887 com_2142_234

Polychronopoulos, Constantine D. Beckmann, Carl Josef 2011-05-07T12:06:43Z 2011-05-07T12:06:43Z 10000-01-01 1993 This thesis examines nonloop parallelism at both fine and coarse levels of granularity in numerical FORTRAN programs. Measurements of the extent of this functional parallelism in a number of FORTRAN codes are presented, as well as compiler and run-time algorithms designed to exploit it. Hardware and software embodiments of the dynamic scheduling algorithms are developed, along with the compiler optimizations necessary to make these practical. The impact of fine grain functional parallelism on instruction-level architecture is explored, and it is shown that dynamic instruction scheduling hardware based on the functional parallelism scheduling algorithms can yield a significant improvement over static scheduling on conventional RISC processors when the latency of memory accesses is highly variable. Measurements of the characteristics of a set of FORTRAN benchmark programs indicates that such a hardware realization is feasible in practice. Made available in DSpace on 2011-05-07T12:06:43Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9411565.pdf: 10241487 bytes, checksum: 69becceaacaae1861f2d49b7c2eeda09 (MD5) Previous issue date: 1993 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:36:47Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:14:57-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9411565 (UMI)AAI9411565 http://hdl.handle.net/2142/19412 eng Copyright 1993 Beckmann, Carl Josef Engineering, Electronics and Electrical Computer Science Hardware and software for functional and fine-grain parallelism text Electrical and Computer Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.