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Hwu, Wen-Mei W. Chang, Po-hua 2011-05-07T12:11:15Z 2011-05-07T12:11:15Z 10000-01-01 1991 This dissertation demonstrates that substantial speedup over that for conventional single-instruction-issue architectures can be achieved by multiple-instruction-issue architectures with the support of an optimizing compiler. We have constructed a full-scale C compiler that can learn the dynamic behavior of user programs by profiling, apply the profile information to guide various code improving techniques, and map the program parallelism onto the parallel architecture. Our base code optimization technology is comparable to today's best commercial C compilers. In addition, we have developed aggressive code generation techniques that are tailored to multiple-instruction-issue architectures. Using our compiler, we have characterized the performance of a large class of multiple-instruction-issue architectures with many important application programs and realistic input data. Made available in DSpace on 2011-05-07T12:11:15Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9136566.pdf: 10956206 bytes, checksum: e8ba8fd254a06094186b198ebace769d (MD5) Previous issue date: 1991 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:37:49Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:15:37-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9136566 (UMI)AAI9136566 http://hdl.handle.net/2142/19554 eng Copyright 1991 Chang, Po-hua Engineering, Electronics and Electrical Computer Science Compiler support for multiple-instruction-issue architectures text Ph.D. Electrical and Computer Engineering Electrical Engineering University of Illinois at Urbana-Champaign Dissertation