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1992 Fuchs, W. Kent Shi, Weiping 2011-05-07T12:19:02Z 2011-05-07T12:19:02Z 10000-01-01 In this thesis, several design, analysis and reconfiguration problems in defect-tolerant VLSI and parallel processor arrays are studied. The NP-hard memory array reconfiguration problem is formulated as a random graph problem, and a provably average-case polynomial time algorithm is presented, while all previous memory reconfiguration algorithms were given without an average-case time complexity analysis. The implemented algorithm runs faster than existing heuristics when the problem size is large. For reconfigurable pipelines, an analytical estimation of the yield is given, while all previous yield estimations were through experiments. A large area defect-tolerant tree architecture is designed that has 99% harvest rate, while all previous designs have harvest rate that is asymptotically 0%. Finally, a general framework for computing the optimal spare allocation is developed for many VLSI redundant systems. Made available in DSpace on 2011-05-07T12:19:02Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9305693.pdf: 2567841 bytes, checksum: 11dc8f0d4cc327db0e1b215c32ef64b8 (MD5) Previous issue date: 1992 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:39:32Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:16:41-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9305693 (UMI)AAI9305693 http://hdl.handle.net/2142/19803 eng Copyright 1992 Shi, Weiping Engineering, Electronics and Electrical Computer Science Design, analysis and reconfiguration of defect-tolerant VLSI and parallel processor arrays text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.