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Saab, Daniel G. Mathew, Ben 2011-05-07T12:33:20Z 2011-05-07T12:33:20Z 10000-01-01 1994 To reduce total chip production costs, circuits must be more testable. Several design for testability (DFT) schemes which trade off various design parameters have been proposed towards that end. The primary focus of this research is a technique called partial reset (PR). Rather than allowing all memory elements in a sequential circuit to be reset by a primary input, only a subset of them is given the capability to reset. Partial reset can assist in initializing the circuit and in providing additional controllability to the circuit. Partial reset has less hardware overhead and typically smaller test application times than scan design. Partial reset, furthermore, allows unrestricted at-speed testing. The tradeoff is in slightly lower testability. Methods of selecting the flip-flops to be reset and the associated reset values are presented. A scheme utilizing multiple reset lines is shown to raise the controllability in the circuit. A dynamic flip-flop selection method is described utilizing a fast sequential test generator. The automated system developed in this research works closely with the test generator to insert PR, observability enhancements and partial scan into a given circuit. The result is higher fault coverage than is possible with PR alone and faster test application times than scan design. Made available in DSpace on 2011-05-07T12:33:20Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9512479.pdf: 4267069 bytes, checksum: 9e1370f23c03a1b81495b01e5f4572a2 (MD5) Previous issue date: 1994 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:42:34Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:18:31-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9512479 (UMI)AAI9512479 http://hdl.handle.net/2142/20241 eng Copyright 1994 Mathew, Ben Engineering, Electronics and Electrical Computer Science Enhancing testability of VLSI circuits using partial reset techniques text Electrical and Computer Engineering Engineering, Electronics and Electrical Electrical and Computer Engineering University of Illinois at Urbana-Champaign Dissertation Ph.D.