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oai:www.ideals.illinois.edu:2142/20438 2023-07-10 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Campbell, Roy H. Murakami, Gary James 2011-05-07T12:39:12Z 2011-05-07T12:39:12Z 10000-01-01 1991 This research investigates packet switching with gigabit-per-second ports for integrated broadband services. The Pulsar switch design is based on a fast word-parallel shift-register ring, and it is a platform for studying the fundamentals of packet switching. With simple First-Come-First-Served (FCFS) input queues, the phenomenon of Head-Of-Line (HOL) blocking lowers throughput. Simulation and analysis of several design alternatives illuminate the problem. A spectrum of queue configurations is constructed from the preliminary studies. Results confirm that non-blocking throughput can be reached with output queueing or with non-FCFS input queueing. Per-destination subqueues at each input port achieve non-blocking throughput with minimal queue memory bandwidth. With a trivial queue service discipline, a flood of best-effort data traffic can obstruct bandwidth-sensitive video traffic. The Pulsar bandwidth accounting algorithm adjusts the priority of each stream based on whether it is below or above its allocation. A multiple-token medium-access-control mechanism implements prioritized round-robin service, and it can be extended to order traffic classes sensitive to delay or jitter. These developments form a service discipline for distributed queues that guarantees allocated bandwidth. The Pulsar switch can be implemented easily with existing technology, and it compares favorably with other high-throughput switch designs. The design can be applied to both network switches and computer backplanes which require low latency and feedback control paths. The research covers the fundamentals of high-speed packet switching including queue configurations for non-blocking throughput, and queue service discipline and medium-access control for allocated bandwidth. The research breaks new ground by combining non-blocking throughput and allocated bandwidth into a switch design for integrated broadband services. Made available in DSpace on 2011-05-07T12:39:12Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9210928.pdf: 3979743 bytes, checksum: cbcc7d29939c22b5f43e1ec8fa9f7a66 (MD5) Previous issue date: 1991 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:43:54Z Item is restricted indefinitely. Restriction data tranferred 2014-07-01T11:19:15-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9210928 (UMI)AAI9210928 http://hdl.handle.net/2142/20438 eng Copyright 1991 Murakami, Gary James Computer Science Nonblocking packet switching with shift-register rings text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.