2026-09-22T02:22:44Z https://www.ideals.illinois.edu/oai-pmh

oai:www.ideals.illinois.edu:2142/20542 2023-07-10 col_2142_5131 col_2142_10761 com_2142_5130 com_2142_10755 com_2142_234

Restriction data tranferred 2014-07-01T11:19:38-05:00 Original Data Group with Access UIUC Users [automated] Release Date: none Reason: ETDs are only available to UIUC Users without author permission ETDs are only available to UIUC Users without author permission U of I Only AAI9210989 (UMI)AAI9210989 http://hdl.handle.net/2142/20542 eng Liu, C.L. Shih, Yung-Ho 2011-05-07T12:42:14Z 2011-05-07T12:42:14Z 10000-01-01 1991 A new approach to MOS circuit fast timing simulation is shown in this thesis. A generic MOS circuit primitive is shown along with the exact analytic solution of its state equation, a nonlinear Ricatti equation. A fast timing digital CMOS circuit simulator ILLIADS has been developed using the generic circuit primitive as well as its exact analytic solution. ILLIADS has been shown to be superior to other fast MOS timing simulators tested in both accuracy and speed. A modified waveform relaxation method for handling circuits with feedbacks is also presented in this thesis. A new algorithm taking advantages of event-driven technique and waveform relaxation method has been developed and applied. With this algorithm, simulation of a collection of ISCAS89 benchmark circuits reveals that the speedup of ILLIADS over SPICE is roughly 3N, where N is the number of transistors in a circuit. To incorporate the channel length modulation effect, an accurate and efficient method has also been developed. With this method, channel length modulation is handled with only a 10% speedup penalty. ILLIADS has been able to simulate a combinational circuit consisting of 235,000 transistors for one cycle output in 10.5 minutes real time in a workstation environment. Also presented in the thesis is a new first-time approach to fast circuit reliability simulation using a simple damaged transistor model. The new approach has made possible accurate and fast reliability simulation of large MOS circuits. Made available in DSpace on 2011-05-07T12:42:14Z (GMT). No. of bitstreams: 2 license.txt: 4922 bytes, checksum: 910b249b4beec47e7ab768910c8f966f (MD5) 9210989.pdf: 4174702 bytes, checksum: c8b1160d6d0684da82674a0a8c5ca1cc (MD5) Previous issue date: 1991 Item marked as restricted to the 'UIUC Users [automated]' Group (id=2) by Howard Ding (hding2@illinois.edu) on 2011-05-07T14:44:35Z Item is restricted indefinitely. Copyright 1991 Shih, Yung-Ho Engineering, Electronics and Electrical Computer Science Computationally efficient methods for accurate timing and reliability simulation of ultralarge MOS circuits text Computer Science Computer Science University of Illinois at Urbana-Champaign Dissertation Ph.D.